The invention relates to an integrated circuit with a non-volatile random access memory cell. The art of designing standard CMOS memories has experienced the usefulness of memory cells that would feature battery-less storage retention combined with the selective programmability thereof. Such would enhance the flexibility of the overall memory. In the ambit of the present invention this feature will be termed "non-volatility", and the invention thereby provides NVSRAMs and NVDRAMs. In contradistinction thereto, battery-supported non-volatility will not be considered herein. The cell configuration considered hereinafter should be programmable in a relatively late stage of the manufacturing process, as distinguished from mask-programmed ROMs that are programmed on a batch level through modifying the geometrical configuration of a cell, or of an array of such cells. In fact, the programming of the present invention is effectable during the post-manufacturing test phase. Moreover, the programming should not need the providing of additional bondings etcetera, such as would be necessary for fuse-programming. In fact, the latter scheme is feasible only for low numbers of programmable cells.
U.S. Pat. No. 4,095,281 describes a memory cell that includes a pair of floating-gate memory devices in its load circuit. This feature provides the capability of non-volatile data storage and by itself may be termed an NVSRAM. However, although the operation of the device appears suitable, the additional floating gates necessitate a series of extra process steps that by themselves would be necessary only for the relatively low number of programmable cells. In consequence, the manufacturing process is relatively uneconomical.
In prior art in general, the major part of an electronic circuit may be manufactured in a standard CMOS process, whilst incorporating several programmable non-volatile memory cells. Using the programmability feature would necessitate however to implement all of the circuit by therein incorporating the appropriate non-volatility option, which renders the chip more expensive. According to the present invention, costs may be lowered through executing also the programmable cells in a standard process, even if this would mean that their size could be appreciably greater than that of the standard cells. In fact, such applies in particular if the number of programmable cells will make up only a small fraction of the overall number of cells.
Potential applications of the feature of the present invention would include the storing of option bits for selectively enabling or non-enabling certain functions in a circuit, storing version numbers and various other identifiers or codes, storing calibration bits for specifying certain analog circuit parameters and modifying of programmed code in a mask ROM. A particular feature of the present invention is that the programming of larger numbers of bits may be effected by inputting them into the SRAM or DRAM through a standard data communication feature such as a data bus. Such bus is clearly a fast communication facility. Eventually, the programming will be made non-volatile or "frozen-in" by an ultra-violet radiation pulse. Also this programming operation may be effected in a fast manner because it could in principle be a parallel mechanism.